Reactive ion etching lag or RIE lag is a frequently seen defect in semiconductor fabrication processes when etching of a line in silicon or silicon oxide is desired. The RIE lag defect affects the etching dimension uniformity and thus the quality of the device fabricated. The RIE lag phenomenon occurs during a dry etching, or reactive ion etching process. The effect is more severe as the line width becomes smaller.
The cause of RIE lag is believed to be a problem occurring because etching rates and profiles depend on feature size and pattern density. RIE lag prevents the achievement of dimensional uniformity after the etching process. In general, microscopic uniformity problems can be grouped into two categories, i.e. aspect ratio dependent etching or pattern dependent etching, also known as microloading. Trench openings with a large aspect ratio etch more slowly than trench openings with a small aspect ratio. The RIE lag or microloading defect becomes more severe when semiconductor devices are fabricated in the sub-micron scale. The term “microloading” also refers to the dependency of etch rates on pattern density for identical features. Microloading results from depletion of reactants because the wafer has a local, higher density unmasked area.
A conventional RIE lag phenomenon is shown in FIGS. 1, 2 and 3. Data shown in these figures were obtained by deep reactive ion etching (DRIE) trenches (FIG. 1) of different sizes ranging between about 2.2 μm and about 5.5 μm. The etch rate measured was in a range between about 1.82 μm/min. and about 2.58 μm/min. The aspect ratios obtained on the trenches that have different lengths and widths are in-between values of 33.1 and 18.7. The reactive ion etching process was conducted by a reactant gas mixture of SF6 at 120 sccm, C4F8 at 85 sccm for a reaction time of 40 min.
As shown in FIG. 1, the etch rate, or the depth of etch, is proportional to the trench size as expected due to RIE lag. The dependency of the etch rate on the trench size is plotted in FIG. 2, while the dependency of the etch rate on the aspect ratio is plotted in FIG. 3.
It is therefore an object of the present invention to provide a method for forming trench openings in semiconductor fabrication that has greatly reduced RIE lag problem.
It is another object of the present invention to provide a method for reducing reactive ion etching (RIE) lag in semiconductor fabrication processes by forming trench openings that have the same planar area.
It is a further object of the present invention to provide a method for reducing RIE lag in forming semiconductor trench openings in a reactive ion etch chamber.
It is another further object of the present invention to provide a method for reducing RIE lag in semiconductor trench forming processes by increasing the chamber pressure in a reactive ion etch chamber.
It is still another object of the present invention to provide a method for reducing RIE lag in a deep silicon etching process for forming trench openings by utilizing an etchant that includes SF6.
It is yet another object of the present invention to provide a method for reducing RIE lag in a deep silicon etching process for forming trench openings by utilizing alternatingly an etchant gas and a passivation gas that includes C4F8.